1. Field of the Invention
The present invention relates to communication and/or computer systems and, more specifically, to circuits for detection and recovery from loss of frequency lock between two system clocks.
2. Description of the Related Art
FIG. 1 shows a block diagram of a prior-art frequency-lock detector (FLD) 100. FLD 100 receives two clock signals, a reference clock signal 110 and a target clock signal 120, and generates a lock-indicator signal 150, which indicates whether the frequency difference between the received clock signals is within a selected tolerance interval. For example, if the frequency difference is within the tolerance interval, then lock-indicator signal 150 is a binary zero. Alternatively, if the frequency difference is outside the tolerance interval, then lock-indicator signal 150 is a binary one. Based on lock-indicator signal 150, a corrective action can be taken, e.g., to adjust the frequency of target clock signal 120, thereby substantially synchronizing that clock signal with reference clock signal 110.
FLD 100 has two equal-limit counters, a reference counter 112 and a target counter 122 clocked by reference clock signal 110 and target clock signal 120, respectively. More specifically, reference counter 112 counts periods (e.g., pulses) in reference clock signal 110 and, based on the count, generates a control signal 114 applied to target counter 122. Similarly, target counter 122 counts pulses in target clock signal 120. When reference counter 112 has counted a selected number of periods (hereafter referred to as a reset-count value), control signal 114 configures target counter 122 to stop its count and to output the count result via an output signal 124. In addition, both counters 112 and 122 are reset to their respective start values and resume counting periods in clock signals 110 and 120, respectively.
Signal 124 having the count result of target counter 122 is applied to comparators 130a-b configured to compare that count result with upper and lower bounds, respectively, corresponding to the tolerance interval. More specifically, signal 124 is applied to the negative input of comparator 130a, while the positive input of that comparator receives an upper-bound signal 126 having the upper-bound value. In addition, signal 124 is applied to the positive input of comparator 130b, while the negative input of that comparator receives a lower-bound signal 128 having the lower-bound value.
Each of comparators 130a-b is designed such that the comparator's output is (i) a binary zero, if the value corresponding to the positive input is greater than the value corresponding to the negative input, and (ii) a binary one, if the value corresponding to the positive input is smaller than or equal to the value corresponding to the negative input. Thus, if the count result provided by signal 124 falls outside the count interval defined by signals 126 and 128, then at least one of comparators 130a-b generates a binary one. In contrast, if the count result provided by signal 124 is within the count interval, then both comparators 130a-b generate binary zeros.
The output signals generated by comparators 130a-b are then applied to a logic-OR gate 140, which generates lock-indicator signal 150. Therefore, if one of comparators 130a-b generates a binary one, then gate 140 also generates a binary one, thereby indicating that target clock signal 120 is out of frequency lock with reference clock signal 110. Alternatively, if both comparators 130a-b generate binary zeros, then gate 140 also generates a binary zero, thereby indicating that target clock signal 120 is substantially frequency-locked with reference clock signal 110.
The reset-count value of reference counter 112 and the width of the count interval established by signals 126 and 128 control the accuracy with which FLD 100 determines the absence or presence of frequency lock between clock signals 110 and 120. For example, if the reset-count value is 10,000 and the width of the count interval is set to 2 counts (e.g., by setting the lower- and upper-bound values to 9,999 and 10,001, respectively), the accuracy of the frequency-lock determination is ±100 ppm. On the other hand, if the reset-count value is reduced to 2,000, the same width of 2 counts of the count interval (e.g., obtained by setting the lower- and upper-bound values to 1,999 and 2,001, respectively) results in the accuracy of the frequency-lock determination of only ±500 ppm.
It is clear from these examples that, to provide a desired accuracy for the frequency-lock determination, FLD 100 has to use at least a certain minimum reset-count value related to that accuracy in reference counter 112. For example, as already indicated above, to provide an accuracy of about ±100 ppm, FLD 100 has to use a reset-count value of at least about 10,000. Due to this limitation, the amount of time (hereafter referred to as latency time) taken by FLD 100 to generate an initial value for lock-indicator signal 150 is at least about a period of reference clock signal 110 multiplied by the minimum possible reset-count value. For example, if reference clock signal 110 has a period of about 10 ns (a frequency of about 100 MHz), latency time corresponding to an accuracy of ±100 ppm is at least about 100 μs. Furthermore, latency time of FLD 100 also affects the number of updates of lock-indicator signal 150 that the FLD can generate per unit time (hereafter referred to as throughput rate). In the above example of 100-MHz reference clock signal 110 and 100-ppm accuracy of the frequency-lock determination, FLD 100 has a throughput rate of about 10,000 updates per second.
For many applications, e.g., data rate negotiation between a transmitter and a receiver, it is often desirable to have a relatively short latency time and/or relatively high throughput rate while, at the same time, satisfying a relatively stringent accuracy constraint for the frequency-lock determination. It is therefore desirable to have an FLD having improved characteristics compared to those of FLD 100.